The present invention relates to integrated circuit devices and methods for manufacturing the same.
Various integrated circuit devices, including semiconductor memory devices such as DRAMs, include a resistor pattern. For example, a resistor pattern may be provided having a resistance chosen to control a signal transmission characteristic of the integrated circuit device. The resistor pattern may be formed, for example, using a polysilicon layer having a specific resistance of thousands of microohms (μΩ) per centimeter (cm) (μΩ•cm).
The resistor pattern for a semiconductor memory device, such as a DRAM, may be formed in a circuit including a capacitor. The resistor pattern may be formed by patterning an upper capacitor electrode material layer and a doped polysilicon layer, which are sequentially stacked on a substrate of the device, using a single mask before a metal conductive line is formed. Such an approach may be used as it is generally relatively easy to control a thickness of the polysilicon layer to control the resistance value of the resistor pattern. Furthermore, the resistor pattern is typically formed after a high temperature heating process that also may affect the resistance value of the resistor pattern.
However, a problem may arise where the upper capacitor electrode is a low resistance material, such as a material having a specific resistance of several μΩ•cm up to hundreds of μΩ•cm. Examples of such materials include ruthenium (Ru), platinum (Pt), and the like. Where such a material is present, its low resistivity characteristics may limit the ability to provide a desired resistance value for the resistor pattern. To form a resistor pattern having a desired resistance value, the resistor pattern may have to be formed with a relatively thin thickness or with a relatively long length to provide a desired resistance given the low specific resistance of the material. Therefore, it is generally not possible to simultaneously form such an upper capacitor electrode and a polysilicon layer providing sufficient resistance.
An example of a resistor pattern for use in a conventional semiconductor memory device will now be described with reference to the cross-sectional view of FIG. 1. As shown in FIG. 1, an upper capacitor electrode 11, having a relatively low resistance value, is formed on a semiconductor substrate 10. A doped polysilicon layer 12 is formed on the other side of the upper capacitor electrode 11. The polysilicon layer 12 can have a structure including a barrier metal of, for example, titanium nitride (TiN). As discussed above, the upper capacitor electrode 11 may be, for example, Ru or Pt. Thus, the resistor pattern in such a configuration may have the following structure: Ru/polysilicon, Pt/polysilicon, Ru/TiN/polysilcon, and/or Pt/TiN/polysilicon.
In such a conventional resistor pattern, because the doped polysilicon layer 12 is formed on an upper capacitor electrode 11 that has a relatively low resistance value (compared to the doped polysilicon layer 12), an electrical current passing through the resistor pattern may substantially flow to the upper capacitor electrode 11 because of its relatively low resistance value. Thus, the ability to increase the resistance value of the resistor pattern based on the resisistivity of the higher resistance value polysilicon layer 12 may be very limited. To avoid this problem, the doped polysilicon layer is generally not formed using the same mask as used to form the lower resistivity upper capacitor electrode 11.